Abstract
In view of its advantages in certain situations over a recursive arrangement, the CCD implementation of a nonrecursive integrator is considered. Transfer inefficiency effects make it virtually essential to adopt a parallel-transfer approach. An implementation is proposed which requires only commercially available CCD delay lines together with conventional analog and digital techniques for driving and addressing the CCDs. An experimental simulation has established the feasibility of this approach. Investigations of the distortion inherent in one version of the integrator and of the integration improvement attainable are in good agreement with theory.
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