Investigation of Operation of Silicon CCD Delay Lines.

Abstract

Abstract : Theoretical analysis of input/output circuit operation for high frequency CCDs has been completed and a computer program for the analysis of various input/output schemes has been written. Initial analysis shows that potential equilibrium method, when operated at high speeds, will cause a residual charge to remain in 'zero' wells - essentially introducing an unintentional fat zero. This effort primarily reduces the available dynamic range; even at a .5 nanosecond equilibration time only a 1 to 2 percent nonlinearity is introduced. In 2.5 to 4 nanoseconds excess noise in this process is reduced to the thermal noise level. Chip design for the high speed CCD delay line is finished and masks are being fabricated. In addition to the 256 bit delay line with the Raytheon proposed ECMOS (Etched Channel MOS) I/O, the chip contains test structures of 64 stage delay lines, with differnet ratios of storage to transfer cell length; and both ECMOS and conventional MOS clock drivers.