A non-linear pattern generator for testing digital VLSI circuitry

Abstract

A digital pattern generator suggested by the boundary scan structure was examined using Fortran simulation. The scan register is closed to form a circular shift register. Each logic output is exclusive-ored between two boundary scan stages. The resulting circuit is a large, usually non-linear, sequential circuit suitable for built-in self- test. Earlier analysis using an independent input model demonstrated that this circular form will provide a rich collection of input test patterns. Our simulation indicates that typical circuits perform even better as pattern generators than the independent model predicts. Specifically the minimum sequence length necessary to cover all possible combinations of K variables was observed to be half or less than the length obtained from the independent model.