Hybrid type test pattern generator for memory testing

Abstract

This paper describes Hybrid type Built in Self-Test Pattern Generator which is employed for identifying all easy to detect as well as hard to detect faults that will occur in memories. The testing of memory by the proposed Hybrid BIST TPG is carried under two phases. In the first phase of testing MLTRTPG is employed to identify easy to detect faults. And other phase of testing is carried out by Adder based 3-Weighted Random Test Pattern Generator (A3-WRTPG) to detect all RPRF's that are dropped by MLTRTPG. The proposed Hybrid type of BIST-TPG can effectively reduce peak power and average power consumption at test time. The proposed BISTTPG also achieves very high fault coverage. Experiments conducted on memory architectures like RAM and ROM convey fact that the proposed Hybrid Type of Built in self- test TPG is successful in achieving power saving, while achieving 100% fault coverage.