Abstract
As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).
Highlights
As a result of the fusion of 3D-Integrated Circuits (3D-ICs) and the mesh-based Network-on-Chips (NoCs), the 3D-Network-on-Chip (3D-NoC) paradigm [1] is considered to be one of the most promising architectures for IC design by providing a highly scalable multi/many-core infrastructure
Based on the clustering fault model, we present the distance-aware Extended Parity Product Code (EPPC) to reduce the needed additional matrices
EVALUATION The EPPC circuit is designed in Verilog-HDL with 45nm process technology
Summary
As a result of the fusion of 3D-Integrated Circuits (3D-ICs) and the mesh-based Network-on-Chips (NoCs), the 3D-Network-on-Chip (3D-NoC) paradigm [1] is considered to be one of the most promising architectures for IC design by providing a highly scalable multi/many-core infrastructure. Dang et al.: Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip (2) information redundancy such as coding techniques [10], [15], [16] or re-transmission request [17]; or (3) algorithm-based fault-tolerance [1], [18], [19]. Despite having multiple methods for detection and correct faults in wires/links, there are two main problems as follows:. Online testing such as Error Correction Code can provide immediate results; it is limited by a certain number of detectable faults. In this paper, we propose a new coding method named Extended Parity Product Code (EPPC), which is specially designed for correcting one defect and detecting multiple defects in TSV links.
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