A new test set compression scheme for circular scan

A new test data compression scheme for circular scan architecture is proposed in this paper. A stochastic heuristic based bio-inspired optimization approach namely ant colony algorithm (ACO) is applied after modification and customization to improve compression efficiency. In circular scan architecture, test data compression is achieved by updating the conflicting bits between the most recently captured response and test vector to be applied next. The quantity of conflicting bits also manifests the Hamming distance between the most recently captured response and the next test vector. A significant reduction in test data volume and test application time is achieved by reducing Hamming distance. The problem is renovated as a traveling salesman problem (TSP). The test vectors are presumed as cities and Hamming distance between a pair of test vectors is treated as intercity distance and a modified ACO algorithm in combination with mutation operator is applied here to resolve this combinatorial optimization problem. The experimental results confirm the efficacy of this approach. An average improvement of 6.36% in compression ratio and 4.77% in test application time is achieved. The exhibited technique sustains an optimal level of performance without incurring any extra DFT (design for testability) cost.

Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

Power dissipation during testing is substantially higher than during normal operations due to increased switching activity. Test vector ordering is an effective method to reduce switching activity in combinational circuits and scan chain reordering has been often cited as an effective technique for reducing power dissipation in the scan chain during testing. This paper describes a technique for re-ordering of test vectors and scan cells to minimize power dissipation in full scan combinational circuits during test application. The reduction is achieved by decreasing the switching activity and spurious transitions between consequent test vectors and scan cells. We formulate the test vector and scan reordering problem as a travel salesman problem (TSP) using hamming distance between test vectors and scan cells. One of the successful approaches to solve TSP is using genetic algorithm (GA) and we use standard genetic algorithm to solve this problem. Experiments performed on the ISCAS-85 and ISCAS-89 benchmark suite show a reduction in power test applying (41% for s298) as well as a reduction in power test vector inserting (25% for s298)

Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

Testing is used to ensure high quality chip production. High test quality implies the application of high quality test data; however, the technology development has lead to a need of an increasing test data volume to ensure high test quality. The problem is that the test data volume has to fit the limited memory of the ATE (Automatic Test Equipment). In this paper, we propose a test data truncation scheme that for a modular core-based SOC (System-on-Chip) selects test data volume in such a way that the test quality is maximized while the selected test data is guaranteed to met the ATE memory constraint. We define, for each core as well as for the system, a test quality metric that is based on fault coverage, defect probability and number of applied test vectors. The proposed test data truncation scheme selects the appropriate number of test vectors for each individual core based on the test quality metric, and schedules the transportation of the selected test data volume on the Test Access Mechanism such that the system-s test quality is maximized and the test data fits the ATE-s memory. We have implemented the proposed technique and the experimental results, produced at reasonable CPU times, on several ITC-02 benchmarks show that high test quality can be achieved by a careful selection of test data. The results indicate that the test data volume (test application time) can be reduced to about 50% while keeping a high test quality.

Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the scan chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also scan chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.

Fast and energy-frugal deterministic test through efficient compression and compaction techniques

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

This paper proposes a new test compression technique that employs a fan-out scan chain with feedback (FSCANF) architecture. It allows us to use prelude vectors to resolve dependencies created by fanning out multiple scan chains from a single scan-in pin. This paper describes the new proposed architecture as well as the algorithm that generates compressed test vectors using a vertex coloring algorithm. The distribution of specified bits in each test pattern determines the compression ratio of the individual test pattern. Therefore, our technique optimizes the overall compression ratio and shows higher reduction in test data and application time than previous techniques, which use the extreme case of serializing all the scan chains in the presence of conflicts across the fanout scan chains. The FSCANF architecture has small hardware overhead and is independent of scan cell orders in the scan chains. Experimental results show that our technique significantly reduces both the test data volume and test application time in six of the largest ISCAS 89 sequential benchmark circuits compared to the previous techniques.

This paper proposes a new test compression technique that employs a fan-out scan chain with feedback (FSCANF) architecture. It allows us to use prelude vectors to resolve dependencies created by fanning out multiple scan chains from a single scan-in pin. This paper describes the new proposed architecture as well as the algorithm that generates compressed test vectors using a vertex coloring algorithm. The distribution of specified bits in each test pattern determines the compression ratio of the individual test pattern. Therefore, our technique optimizes the overall compression ratio and shows higher reduction in test data and application time than previous techniques, which use the extreme case of serializing all the scan chains in the presence of conflicts across the fanout scan chains. The FSCANF architecture has small hardware overhead and is independent of scan cell orders in the scan chains. Experimental results show that our technique significantly reduces both the test data volume and test application time in six of the largest ISCAS 89 sequential benchmark circuits compared to the previous techniques.

Recently design for manufacturability (DFM) has been required to achieve higher process yield. Information obtained from silicon by testing and/or fault analysis is sometimes fed back for redesign of VLSI circuits. In this paper we propose a method to maximize defect coverage of a test set initially generated for stuck-at faults in a full scan sequential circuit by using feed back information from fault analysis. If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. The proposed method improves defect coverage of the test set by not adding new test vectors but modifying test vectors with the information obtained from fault analysis. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND/OR-type bridging faults. Experimental results show that the proposed method significantly decreases the number of non-feedback AND/OR-type bridging faults undetected by a test set generated for stuck-at faults.

If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. In this paper we propose a method to detect bridge defects with a test set initially generated for stuck-at faults in a full scan sequential circuit. The proposed method doesn't add new test vectors to the test set but modifies test vectors. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND-type, OR-type and 4-way bridging faults, respectively. Experimental results show that the proposed method increases the defect coverage.

This paper proposes a novel approach to core based SoC test compression. Research works show that almost all the test vectors have the same part in common. Therefore there exists such a vector, from which parts of each test vector from the different test sets can be sought. Based on this, first we attempt to find a vector named overlapped vector which contains parts of each test vector and has shorter length than that of the sum of each test vector's length. Second the overlapped test vectors are further compressed utilizing frequency-directed run-length (FDR) coding. Due to the fact that the test application time is proportional to the length of test vector, our proposal achieves as short test time as possible. Experimental results demonstrate that the proposed method obtains reduced test application time and significant test data compression rate.