A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications

Abstract

This paper reports a modified latch based Sense Amplifier (SA) and then provides a qualitative statistical comparison of its yield based on offset voltage and sensing delay in 28nm CMOS technology. A thorough comparative statistical analysis with regards to conventional latch based SA is also reported with respect to random do pant fluctuation. Influence of design parameter like sizing of the devices on sensing delay has been analyzed based on Design of Experiments (DoE). Furthermore, the effects of random variations on the offset of both the conventional and proposed SAs have been investigated using Monte Carlo analysis. The proposed SA architecture exhibits 39% improvement in the sensing delay and 6.5% improvement in the offset voltage at supply voltage of 1V when compared to the conventional SA. An optimal scheme to design and operate the proposed SA topology for achieving improved offset voltage and sensing delay is also suggested.