Abstract
Three-dimensional (3-D) integration based on the through silicon via (TSV) technology involves the processes of wafer thinning, TSV etching and plating, re-distribution layer (RDL) formulation, and FC chip bonding. TSV plating is a key to the 3-D electrical interconnection, whereas the prewetting process is one of the important factors that can decide the filling depth and quality of the TSV plating. In this paper, a new three-step prewetting process with high efficiency and low cost is developed and includes absolute ethanol infiltration, deionized water washing, and a copper electrolyte bath. In the electroplating process, blind vias with an aspect ratio of 10:1 prewetted by our three-step prewetting process were fully filled. [2018-0190]
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