A new poly-silicon MOS transistor model which includes the effects of bulk trap states in grain boundary regions

Abstract

In this paper we report a simple poly-silicon MOS transistor model which includes the effects of bulk trap states in grain boundary regions. The introduction of numerous gate interface states or carrier mobility deterioration is not essential to our model, in which a poly-silicon MOS transistor is modelled as a hybrid transistor consisting of a conventional transistor and a newly modelled transistor. We assume here that the conventional MOS transistor model can be applied for the single crystal regions of individual poly-silicon grains. Our new model is used for the grain boundary regions. We also assume that there exist neutral bulk trap states uniformly distributed within the band gap of grain boundary regions and that the number of charged trap states is proportional to the potential at any point. The solutions of Poisson's equation in the grain boundary region show that the potential distribution is not parabolic but hyperbolic, and that the threshold voltage increases rapidly as the trap density increases. The general equation for calculating surface potential is given; during weak inversion, it may be expressed as a function of trap density, decreasing as that density increases. In order to model the subthreshold characteristics of the hybrid transistor, we have calculated both the diffusion current and the amount of injection charge due to extended thermionic emission from the single crystal region to the grain boundary region. The linear characteristics are calculated by using the threshold voltages and the total thicknesses of the single crystal and grain boundary regions.