Abstract
Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an optimization method are high performance, low power usage and small area (PPA). Therefore, any new optimization technique should improve at least one, if not all, of these requirements. This paper proposes a new low-power methodology, applying a MBFF merging solution during the physical implementation of an IC to achieve better power consumption and area reduction. The aim of this study is to prove the benefit of this methodology on the power saving capability of the system while demonstrating that the proposed methodology does not have a negative impact on the circuit performance and design routability. The experimental results show that MBFF merging of 76% can be achieved and preserved throughout the entire physical implementation process, from cell placement to the final interconnection routing, without impacting the system’s performance or routability. Moreover, the clock wirelength, nets and buffers needed to balance the clock network were reduced by 11.98%, 3.82% and 9.16%, respectively. The reduction of the clock tree elements led to a reduction of the power consumption of the clock nets, registers and cells by 22.11%, 20.84% and 12.38%, respectively. The total power consumption of the design was reduced by 2.67%.
Highlights
The increase in modern integrated circuit (IC) performance and functionalities due to the rapid evolution of nanotechnology has made power consumption a major challenge for all integrated circuits (ICs) providers [1]
The evolution of technology has resulted in very high transistor density, which has led to an increase in complexity, especially with respect to the Internet of Things (IoTs), automobiles, cell phones, medical equipment and networking IC market segments [2]
It is important to be conscious of power usage throughout the entire design process, from the architecture through all the circuit conception phases, to maximize high performance, low power consumption and small area size (PPA) [3]
Summary
The increase in modern integrated circuit (IC) performance and functionalities due to the rapid evolution of nanotechnology has made power consumption a major challenge for all IC providers [1]. The main focus of this research is to enhance the physical implementation process of an IC by implementing multi-bit flip-flop (MBFF) merging at the end of the standard cell placement phase, subsequently performing the clock tree synthesis and finishing with the final routing and post-routing optimization. The previous literature mainly presented the MBFF merging method without studying its impact on the physical design process and its beneficial effects on reducing power consumption. This paper proposes a new low-power methodology that performs MBFF merging via an enhanced algorithm at the end of the cell placement stage and subsequently, performs the remaining physical implementation stages, including the final routing. The main objective was to reduce the total consumed power by applying MBFF merging at the physical implementation stage instead of using the standard, power-driven place and route process. FF merging should be performed at the end of the “place” stage
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