Abstract
A PMOSFET degradation phenomenon induced by gate current in the off-state condition was studied experimentally for single-drain and lightly-doped-drain (LDD) structures. It is found that scaling down the gate length causes the gate bias condition where the fastest degradation is observed to shift from a condition of maximum gate current to one of zero gate voltage. This indicates a new constraint for scaling PMOSFETs. The hot-electron induced punchthrough (HEIP) effect has been considered one of the serious constraints for utilizing the single-drain structure, as well as for high-voltage applications. Effective channel length can be reduced significantly by HEIP effects in the on-state condition, but once the off-state drain leakage current increases, the off-state stress becomes more severe than the on-state HEIP effect
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