Abstract

A sign detection is a non-modular operation in the residue number system (RNS), that requires calculating a position characteristic of the number represented in RNS. This paper proposes a new method of sign detection based on the Chinese remainder theorem (CRT) with fraction values. A hardware modeling on FPGA for the proposed method shows that it requires 1.4 - 30.9 times fewer hardware costs compare with CRT based method and 5.9 - 42.2 times fewer hardware costs compare with the method based on mixed radix conversion based. The proposed method of sign detection can be used in RNS based devices to implement magnitude comparison and division operations.

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