A New Method^ of Reconfigurable ADC with Automatically Optimized Parameters

Abstract

Reconfigurable analog to digital converter (ADC) has been designed and constructed based on the new method proposed in this paper. The most important part of the reconfigurable ADC is the successive approximation register (SAR) type of ADC whose resolution is controlled based on the maximum signal frequency of the input. This results into the optimum performance with respect to resolution and conversion time of the ADC, since the number of stages of conversion in SAR technique are decided based on the maximum input signal frequency. The rate of change of input is assessed using a circuit designed for this purpose to change the resolution of SAR ADC automatically. An additional flash ADC has been incorporated in the design to extend the range of frequency up to several hundred MHz. The resolution of this hybrid ADC (flash + SAR) is automatically varied from 8-bit to 16-bit according to the maximum input signal frequency. This ADC has been designed and simulated in National Instruments Multisim 14.1, and the simulated results are provided in the paper.KeywordsFlash ADCSAR ADCHybrid ADCRate of change of input