A New Method of Component-level ESD Test to Assess System-level ESD Risk for ICs

Abstract

As components or products become more reliable, the failure by electro static discharge (ESD) is getting one of the most important problems. In the past, ESD was recognized as a system-level problem. However, it has recently been recognized as a component-level problem such as dynamic random access memory (DRAM) and solid state drive (SSD). It is difficult to assess the system-level ESD risk for the components being developed. In this paper, component-level ESD test method is developed using transmission line pulse (TLP) to assess ESD immunity of IC products. In addition, it is verified that ESD immunity of ICs correlated with ESD immunity in system-level. Therefore, system-level ESD performance for the components being developed can be predicted using the new component-level ESD test method. This results in reduced development costs for both system and components.