A new low power multiplexer based ternary multiplier using CNTFETs

Abstract

In the following paper, a single bit ternary multiplier utilizing carbon nanotube field-effect transistor (CNTFET) has been presented. Almost in the ternary circuit design, only one supply voltage VDD is used and a voltage division circuit is activated to produce VDD/2 for logic ‘1’, So the direct current from VDD to ground increases the static power considerably. In This paper, using two supply voltages, VDD and VDD/2, the circuit is designed so as VDD/2 could be transmitted to output directly for logic ‘1’ to eliminate direct current from source to ground. This is provided by proper division of truth table and using two level output gates. Also for extending to multi bit multiplier in this way, three type of half adders and one full adder are designed using two supply voltages and removing direct current. The implementation for two bits is reported. The results of simulation, using Hspice software and Stanford 32 nm CNTFET library with the voltage of 0.9 (v), as expected, indicate much lower power dissipation and power delay product (PDP) in comparison with the previous works.