A New Low-Power Circuit Design Optimization for Image Processing

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A simple-to-implement and easy-to-integrate strategy for image processing is proposed in this paper, which effectively and efficiently optimizes the power consumption of both DRAM and SRAM. Since the power consumption of DRAM is proportional to the number of bit-‘1’s and the power consumption of SRAM is linear relative to the flip probability, the proposed strategy first drops and encodes the image to minimize the number of bit-‘1’s per pixel. The processed data are then decoded, with the flag bit set to “1” to reduce the flip probability. In the experimental simulations, the power consumption of DRAM was reduced by up to 64.88%, while that of SRAM was reduced by up to 62.01%, with negligible circuit costs. In image display applications, the proposed strategy effectively compensates for certain errors in the JPEG system. In image classification tasks, there was only a 1–2% reduction in test set accuracy, demonstrating the superiority of truncation compensation. Additionally, the performance of the robot was negligibly affected by the approximate strategy, which shows the significant potential of the proposed strategy in the field of artificial intelligence and robotics.