Abstract
In the recent trends the need for low power and less on-chip area is on high note for the portable devices. To cope up with the arising need, a new Magnitude Comparator is proposed with low power and less on-chip area for different range of lower supply voltages using Modified GDI technique implemented in 45nm process technology using CADENCE VIRTUSO. There is 95% and 67% reduction in power at lower supply voltage, 70% and 35% less on-chip area w.r.t conventional CMOS and existing GDI comparator respectively.
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