A New High-Speed Memory Interconnect Architecture Using Microwave Interconnects and Multicarrier Signaling

Abstract

A new memory bus concept that has the potential to push double data rate (DDR) memory speed to 30 Gbit/s is presented. We propose to map the conventional DDR bus to a microwave link using a multicarrier frequency division multiplexing scheme. We call this approach multicarrier memory channel architecture (MCMCA). In MCMCA, each memory signal is modulated onto an RF carrier using 64-QAM format. The carriers are then routed using substrate integrated waveguide (SIW) interconnects. At the receiver, the memory signals are demodulated and then delivered to SDRAM devices. We present details of our proposal as well as the results of simulations and experiments, which demonstrate the merits of this approach. Experimental characterization of the new channel shows that by using judicious frequency division multiplexing, as few as one SIW is sufficient to transmit the 64 DDR bits. The overall aggregated bus data rate achieves 240 GB data transfer with the error vector magnitude not exceeding 2.26% and phase error of 1.07 degrees or less.