Characterizing Pattern Dependent Delay Effects in DDR Memory Interfaces

Abstract

Designing high speed Double Data Rate (DDR) memory interface controller in low cost wire-bond packages is a difficult goal to achieve. The interface is limited at speed because of various factors such as Inter Symbol Interference (ISI), Power Delivery Network (PDN) noise, Cross talk etc. At high speeds like 1Gbps, Pattern dependent effects have a major role to play in DDR link budget analysis. Hence, selecting the right data pattern for DDR interface characterization becomes an important problem to solve. Little data exists on what patterns to use for DDR bus characterization and still lesser silicon data exists. This paper is an attempt to create an analysis technique to characterize high speed DDR interfaces. A set of data patterns is proposed. They can be used to characterize any source synchronous parallel bus interfaces like DDR etc. These data patterns simultaneously capture the effects of ISI, PDN noise and Cross talk, the major sources of noise or uncertainty in this case. We have built a case for proving that these patterns are indeed the worst from DDR timing prospective. DDR design space can thus be reduced by concentrating on these worst case data patterns only as compared to the complete set of patterns. Further, silicon results are shared, to prove the efficiency of our approach.