Abstract
This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR) system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS) based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR) of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.
Highlights
In the prevalent audio broadcasting applications like private mobile radio (PMR) and digital audio broadcastingterrestrial (DAB-T) standards, excellent clarity along with the source stability is required for the voice transmission
Xilinx XCV2vp30-7FF896 device has been used as the target device for FPGA implementation, XST has been used as a synthesis tool, and XPower has been used for power calculation
A new high-performance digital Frequency modulation (FM) modulator and a digital phase-locked loop-based FM demodulator have been proposed in this paper
Summary
In the prevalent audio broadcasting applications like private mobile radio (PMR) and digital audio broadcastingterrestrial (DAB-T) standards, excellent clarity along with the source stability is required for the voice transmission. One high-speed, low-power, and reduced-area digital FM modulator has been implemented in the FPGA device to support the audio broadcasting system in software-defined radio (SDR) system. PLL method is one of the popular techniques for FM demodulation It can be implemented in integrated forms, but sudden departure from its linearity property of the VCO in some portions of the frequency range degrades the overall system performance. A reduced-area, low-power, and high-speed linear digital FM demodulator using the DPLL technique [5, 6] has been implemented towards the development of an SDR system. Targeting to the generation SDR-based wireless communication transceiver, in this work all the basic components of DPLL-based FM demodulator are fully optimized without losing the system output behavior in comparison with the previous DPLLbased FM demodulator implementations.
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