A new hardware efficient reconfigurable fir filter architecture suitable for FPGA applications

Abstract

Multistandard wireless communication systems require the reconfigurable FIR filters with low complexity architectures. The complexity of FIR filters is dominated by the coefficient multipliers. It is well known that partial product is an efficient technique to reduce the complexity of coefficient multipliers in high order FIR filters implementation. A new hardware efficient reconfigurable FIR filter architecture is proposed in this paper based on the proposed binary signed subcoefficient method. Using the proposed coefficient representation method, the hardware requirements for multiplexer units are reduced dramatically with respect to typical methods. FPGA synthesis results of the designed filter architecture show 33% and 27% reduction in the resources usage over previously reported two state of the art reconfigurable architectures.