Abstract
A new low power and high speed full adder is designed which targets at tree structured applications. By employing complementary signal at input, buffer inverter at output, a new transmission gate based full adder is proposed. This new adder uses 20 transistors to achieve high driving ability and low power consumption. Simulation in Semiconductor Manufacturing International Corporation 0.18-um CMOS process indicates that the new adder outperforms the four existing adders in terms of power delay product. The design has a full voltage swing, making it suitable for technology scaling. The adder can be used for high-performance circuits such as high speed and low power multipliers.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
