A new energy efficient full adder design for arithmetic applications

Abstract

In the era of advanced microelectronics, designing an energy efficient processor is a prime concern. Full adder is a most crucial unit in digital signal processing applications. This paper addresses the implementation of 1-bit full adder cell. In addition to this, AND and OR gate as an essential entity is also proposed with minimum hardware overhead. The circuit being studied is implemented using Cadence Virtuoso tool in 55-nm CMOS process technology. The simulations are carried out using spectre simulator under various conditions such as different operating frequencies, load capacitors and supply voltages that may occur in realistic conditions. In comparison with the C-CMOS full adder design, the proposed implementation was found to offer 50.24% improvement in power consumption and 26.46% improvement in power delay metric.