A New Electrodeposition Approach for Multicomponent Solder Alloys

Abstract

Enactment and enforcement of international regulations restricting the use of lead-bearing solders has triggered plenty of research on Pb-free alloys for Integrated Circuits (ICs) packaging [1]. Nonetheless, Sn-Pb (63/37) eutectic still possesses unique features (e.g. low melting point, optimum mechanical properties, ideal surface tension allowing for holes and gaps wetting, capability of reducing, inhibiting or eliminating tin whiskers formation, etc.) hardly matched by lead-free solders.Alloys belonging to the SAC (Sn-Ag-Cu) category constitute the most widespread alternative to tin-lead solder because of their relatively low melting point [2], “composition-tunable” wettability [3], and high tensile strength (compared to the Sn-Pb eutectic). Particularly, SAC-305 (Sn = 96.5, Ag = 3, and Cu = 0.5 wt%) and SAC-405 (Sn = 95.5, Ag = 4, and Cu = 0.5 wt%) are by far the most employed solders compatible with the PTH (Plating Through Hole) layers connection method, the SMT (Surface Mounted Technology) components placement approach, and the surface finishes routinely used in PCBs manufacturing (e.g. organic solder preservative, lead-free hot air solder levelling, immersion silver, immersion tin, electroless nickel immersion gold, etc.). Furthermore, near eutectic SAC alloys (i.e. comprising 3-4 wt% of silver and 0.5-1 wt% of copper) also benefit from improved temperature cycling reliability mainly due to the high Ag content.The present work puts forward a new multi-layer electrodeposition technique amenable to wafer level chip scale package. By taking advantage of multiple Dynamic Liquid Drop/Meniscus (DLD/DLM), it is possible to plate binary, ternary and even quaternary solders at high-throughput, high precision and low cost [4]. The DLD/DLM exposes a constantly refreshed confined electrolyte volume in contact with the substrate surface [5]. The core of the method consists in interposing a rinse DLD/DLM into a sequential array of multiple independent electroplating DLD/DLMs (one for each component to deposited). Such a configuration results in a synergistic system composed of different plating outputs (plating head). Thereby, scanning the plating head over the wafer surface allows to coat the substrate with a thin layer of each component. Thus, each plating head pass leads to the deposition of a multilayered structure reflecting the targeted composition of the alloy. In other words, the current density is regulated in each DLD/DLM in order to obtain the desired wt% of every single component in the final solder deposit. Obviously, the total film thickness depends on the number of layers and can be varied in a wide range to allow an homogenous structures even without reflow.As a proof-of-concept, SAC-305 and SAC-405 bumps and caps on top of copper pillars [6] were deposited: 30 μm thick structures were electroplated through more than 350 layers of each element. Bumps as high as 10 µm (attained for net electroplating times as low as 14 seconds) were sectioned by FIB (Focused Ion Beam) to verify the agreement between the expected composition and the actual one. EDX analysis performed before and after reflow proved that the high number of layers produces a compositionally homogenous solder regardless of the metal deposition sequence and reflow temperature. A detailed investigation of SAC and quaternary SAC+Me (e.g. Ni, Zn) alloys composition will be presented (e.g. thermal, mechanical and wetting properties); EDX analysis before and after reflow proving that the high number of layers homogenous solder is obtained independently of metal deposition sequence and even without reflow. Furthermore, the nozzle sizes of the multiple DLD/DLM equipment will be correlated to the aspect ratio of the dry film opening.[1] A. Lancaster and M. Keswani, Integration, 75, 77 (2017).[2] A. B. Frazier, R. O. Warrington and C. Friedrich, IEEE Transactions on Industrial Electronics, 42(5), 423 (1995).[3] X. Xu, A. S. Gurav, P. M. Lessner and C. A. Randall, IEEE Transactions on Industrial Electronics, 58(7), 2636 (2011).[4] K. Kholostov, L. Serenelli, M. Izzi, M. Tucci, D. Bernardi, M.Balucani, IEEE Journal of Photovoltaics 5(2), 404 (2016).[5] M. Balucani, K. Kholostov, P. Nenzi, R. Crescenzi, D. Ciarniello, D. Bernardi, L. Serenelli, M. Izzi, M. Tucci,Energy Procedia, 43, 54 (2013).[6] K. Kholostov, A. Klyshko, D. Ciarniello, P. Nenzi, R. Pagliucci, R. Crescenzi, D. Bernardi and M. Balucani, 43, 2014 IEEE 64th Electronic Components and Technology Conference.