A New Efficient High-Level Synthesis Methodology for Lower Power Design

Abstract

This paper presents a new efficient high-level synthesis methodology for low power design. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, the register allocation algorithm determines the minimum register after the life-time analysis of all variable in allocation algorithm. It is a minimum the switching activity using graph coloring technique for low power consumption. And the supply voltage is reduced a maximal using multiple voltage considering resource constraints. The proposed algorithm proves the effect through various high-level synthesis benchmark to adopt a low power scheduling and allocation algorithm considering in multiple supply voltage.