A new design of adder circuit for low power and high speed in sub-threshold region

Abstract

The paper proposes the design of an adder circuit based on a majority function. The adder comprises of only six metal-oxide-semiconductor (MOS) transistors. To make the design to be used invariably in the system with least nanodevice dimensions, some modifications have been done in the existing adder design. Post-layout simulation result at 45 nm Taiwan semiconductor manufacturing company (TSMC) technology confirms that the proposed design works faithfully in sub-threshold regime with appreciable 7% of area reduction and 23.54% power saving with respect to earlier design.