A New Design-Centering Methodology for VLSI Device Development

Abstract

VLSI yield optimization and centering are two key interests in the development of submicron VLSI's. Accordingly, we have developed a new automation technique based on simulation CAD tools. The features of this methodology are great reduction of simulation time in device optimization, and accurate prediction of process sensitivity in device performance. The approach we used was basically a modification of the design of experiment method. This approach makes it possible to obtain an optimum with a large number of parameters. The methodology was successfully applied to the optimization of a 0.5-μm MOSFET structure based on only a one-day computation by a supercomputer (S-810) using a two-dimensional device simulator. In the centering, we assumed five objective device performances, that is, threshold voltage V/sub TH/, output conductance G/sub D/, drain current I/sub D/, V/sub TH/ dependence on gate length ΔV/sub TH/ / ΔL/sub G/, and maximum substrate current I/ sub submax/. The use of the device centering system predicted an optimized nMOSFET with 0.52-μm gate length, 9.4-nm gate oxide thickness, and 1.6 x 10/sup 16/cm/sup-3/ substrate concentration for a given set of objective performances. Statistical variations of device characteristics were also calculated.