Abstract
In this work, a new multi-term common subexpression elimination (CSE) algorithm is proposed. The new algorithm aims to reduce area-delay-production (ADP) in VLSI designs of constant matrix multiplication (CMM) over binary field. For promoting delays optimization, a gate-level delay computing method is used to compute the delays based on the transformed constant matrices. The new algorithm also takes a greedy algorithm to search the minimal ADP result. The worst case computational complexities of the delay computing method and the new CSE algorithm are analyzed, respectively. Experimental results have shown that the new CSE algorithm has more efficient in ADP reduction in VLSI designs of binary CMM.
Published Version
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