A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs

Abstract

this paper proposes a new reconfigurable architecture for Configuration Logic Block (CLB) in SRAM-based FPGAs. This architecture can correct Single Event Upset (SEU) by utilizing both Triple Modular Redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of Look-Up Table (LUT) in current-day SRAM-based FPGAs; moreover, the proposed architecture uses the same routing architecture which is presented in current-day FPGAs, so all CAD algorithms can be used in the employed design. Experimental results show that the proposed architecture can correct 100% SEU in the configuration memory of CLB without any user intervention or reconfiguration; moreover, the required area and the power consumption are respectively 136% and 195% more than the area and the power consumption that are required by the standard 16 ×1 LUT.