A new capacitive electro-chemical etch-stop technique

Abstract

A new capacitive electro-chemical etch stop (CECES) technique is described that offers easy and robust batch fabrication of selectively-dissolved, lightly-doped silicon microstructures. This technique allows the fabrication of silicon microstructures with minimal internal stress into which electronic circuits may be integrated. The CECES technique utilizes the large capacitance change observed when the semiconductor junction between an epi-layer and the substrate is exposed to the etchant to apply the passivating anodic voltage to create an electrochemical etchstop. It requires only a pulse generator and an on-chip resistor in series with the epi-layer to implement a passivating waveform only after the substrate is dissolved. This technique also completely removes any possibility of premature passivation of the substrate through non-idealities in the n-p junction leakage current and parasitic resistances in the substrate and etchant. Measured results on n-epi on p-substrate wafers have produced nonuniformities less than 1% across a 3 silicon wafer. Additional benefits of CECES are that: (1) batch fabrication is easily achieved (2) there is no need for specialized etchant-resistant jigs to support the wafer in solution, or for dedicated reference electrodes and potentiostats, (3) selective dissolution of the etch stop layer is achieved, and (4) superior etch stop uniformity is achieved.