A New Capacitance-Voltage Model for Hydrogen-Terminated Diamond Mosfet

Abstract

Hydrogen-terminated diamond (HTD) metal-oxide-semiconductor field-effect transistor (MOSFET) is a relatively new electronic device made on diamond substrate. Due to the unique properties of diamond, the device shows comparable performance to those made on III-V compound semiconductors and good potential in radio frequency (RF) and high-power applications [1]. The most distinguishing property of HDT device is that it shows p-type conductivity at the diamond surface even though there is no intentional doping process involved during the fabrication process, and the hole carrier density is high (~1013cm-2) [2]. However, the origin of this p-type conductivity is still not fully understood, and the capacitance-voltage (C-V) characteristics of the HTD MOSFET is quite different from the regular MOSFET devices made on other semiconductor materials such as silicon [3]. In our present work, we derive a device model that takes into account of a surface adsorbate layer (ADL) to study the C-V characteristics of the HTD MOSFET. In this model, the ADL acts like a reservoir of hole carriers and forms a hetero-structure with the hydrogen-terminated diamond surface. Due to the Fermi level difference and band offset between the ADL and diamond, the hole carriers will flow from the ADL into diamond to form the conductive channel. As the gate bias is varied from positive to negative, the C-V curve will go through three different regions viz., depletion, accumulation, and injection regions. In the depletion region, both the ADL and the hole channel at diamond surface are depleted, therefore the gate capacitance is very small. In the accumulation region, the hole carriers are accumulated at diamond surface by the electric field but the ADL is still fully depleted, so the total gate capacitance equals the capacitance of gate oxide and ADL in series. In the injection region, the hole carriers overcome the band offset at the ADL/HTD interface and move into the ADL, which will cause the gate capacitance to increase again. Finally, the gate capacitance will reach its maximum value which equals the capacitance of the gate oxide. Based on our device model, a 2D device simulation is performed by using Sentaurus Technology Computer-Aided Design (TCAD) software and an analytical model is derived. The results from both the device simulation and analytical model show good match with the reported data for a practical device, and thus our model is effective in describing the charge transport inside the device. In addition, the influence of device parameters such as the thickness of gate oxide and hole carrier density on the C-V characteristics is studied, which is helpful in computer-aided design and optimization of future HDT devices.