Abstract
To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V/sub T/ lowering effect and the lateral electric field at the drain. A 0.25- mu m GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V/sub D/=V/sub G/=3.3 V, 1 V higher BV/sub DSS/, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions. >
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