A neuron-MOS neural network using self-learning-compatible synapse circuits

Abstract

A circuit technology for self-learning neural network hardware has been developed using a high-functionality device called Neuron MOS Transistor (/spl upsi/MOS) as a key circuit element. A /spl upsi/MOS can perform weighted summation of multiple input signals and thresholding all at a single transistor level based on the charge sharing among multiple capacitors. An electronic synapse cell has been constructed with six transistors by merging a floating-gate EEPROM memory cell into a new-concept /spl upsi/MOS differential-source-follower circuitry. The synapse can represent both positive (excitatory) and negative (inhibitory) weights under single V/sub DD/ power supply and is free from standby power dissipation. An excellent linearity in the weight updating characteristics of the synapse memory has been also established by employing a simple self-feedback regime in each cell circuitry, thus making it fully compatible to the on-chip self-learning architecture of /spl upsi/MOS neural networks. The basic operation of the synapse cell and a /spl upsi/MOS neural network using the synapse has been experimentally verified using test circuits fabricated by a double-polysilicon CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>