A NAND Flash Memory Controller for SD/MMC Flash Memory Card

Chuan-Sheng Lin,Kuang-Yuan Chen,Yu-Hsian Wang,Lan-Rong Dung

doi:10.1109/icecs.2006.379716

Chuan-Sheng Lin, Kuang-Yuan Chen + Show 2 more

Open Access

https://doi.org/10.1109/icecs.2006.379716

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Abstract

In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit parallel BCH ECC code was designed for correcting the random bit errors of the flash memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (in system programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC flash memory card controller chip was designed and implemented with UMC 0.18mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.

Highlights

AS a semiconductor memory device capable of nonvolatile data storage even after removing the power supply, NAND flash has gained popularity in a variety of applications, like removable memory cards for portable devices, MP3 players, digital still cameras, and mobile handsets
We presented a -EC -bit parallel Bose–Chaudhuri–Hocquengham (BCH) error-correction code (ECC) with incorporating the systolic array architecture
The major functions of the controller can be divided as the -EC -bit parallel BCH ECC circuit, the code-banking structure, and firmware in-system programmability (ISP), the defect management and wear-leveling algorithm, and the dual channel and multi-buffering mechanism

Summary

INTRODUCTION

AS a semiconductor memory device capable of nonvolatile data storage even after removing the power supply, NAND flash has gained popularity in a variety of applications, like removable memory cards for portable devices, MP3 players, digital still cameras, and mobile handsets. The requirement for multiple energy states leaves MLC technology with a lower margin of error to read the bits. Once the number of bad blocks exceeds a certain value that the controller chip can manage, the NAND flash chip is declared fail. A NAND controller is required to handle the bit errors, the bad blocks, maintaining the high data accessing speed, flash memory management, etc. The appropriateness of a NAND controller can enhance the reliability and increase the endurance cycles of the flash memory. The systolic array architecture has been applied to the regular and iterative very large scale integration (VLSI) architecture, like Reed–Solomon (RS) encoders and decoders, and showed good performance [10]. We presented a -EC -bit parallel Bose–Chaudhuri–Hocquengham (BCH) error-correction code (ECC) with incorporating the systolic array architecture. The good performances were shown by the real chip realization

CONTROLLER ARCHITECTURE

Experiment and Test Results

Code-Banking and Various NAND Flash Memory Support

Controller Chip Implementation