A multitechnology test chip for university integrated circuit fabrication projects

Abstract

At Rochester Institute of Technology, a multitechnology test chip has been designed that has been in use for one year. The test chip has been incorporated in most of the fabrication runs, providing a large number of chips for probing. Each wafer processed has 40 test chips and 120 device chips. Each 4000*4000 mu m test chip has seventeen 12 pad cells that contain a variety of test structures. In addition, there are eight cells for optical resolution and overlay structures for the various levels. The test chip has alignment marks for the GCA 4800 wafer stepper, Perkin Elmer scanners, and Kasper 2001 contact aligners. The authors describe the test chip, the structures on it, and the test system, and provide examples of the types of output that have been obtained. >