Abstract
A multiphase delay-locked loop (MDLL) with interleaving calibration has been designed with TSMC 0.18 μm CMOS technology. The proposed interleaving calibration relieves the hardware cost for requirement of high resolution phase detector (PD) effectively in the conventional method with sequential calibration. In addition, the output jitter is improved because of reducing the phase transition states. The core area is 469.4 μm × 471.7 μm and power consumption is 22.6mW at 150 MHz. The measured phase error is reduced to 25ps using interleaving calibration.
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