Abstract
One of the challenging problems in networks-on-chip (NoC) design is optimizing the architectural structure of the on-chip network in order to maximize the network performance while minimizing the corresponding costs. In this study, a method for multi-objective optimization of NoC architecture is presented. The method considers two cost metrics, power and area, and one performance metric, delay. Our method combines the selection of NoC standard architecture and the optimization of the selected architecture based on the information of the NoC mapping. The method is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our method outperform those standard architecture with respect to three metrics: power, delay and area.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call