Abstract

This paper presents a new multilevel converter with a reduced number of power components for medium voltage applications. Both symmetric and asymmetric structures of the presented multilevel converter are proposed. The symmetric topology requires equal dc source values, whereas the asymmetric topology uses minimum switch count. However, both structures suffer from high blocking voltage across the switches. To reduce the blocking voltage on switches, an optimal topology is presented and analyzed for the selection of the minimum number of switches and dc sources, while maintaining a low blocking voltage across the switches. A comparative analysis with recently published topologies was performed. The simulation results, as well as the comparative analysis, validated the robustness and effectiveness of the proposed topology in terms of the reduced power loss, lowered number of components, and cost. Furthermore, in addition to the simulation results, the performance of the proposed topology was verified using experimental results of 9, 17, and 25 levels.

Highlights

  • In recent years, utilization of multilevel inverters (MLIs) has increased in different applications such as renewable energy systems, utility interfacing schemes, automotive applications, and adjustable speed drives

  • The CHB-MLI topology can be configured in both symmetric and asymmetric configurations

  • A new cascaded diode half-bridge multilevel inverter topology is presented in symA new cascaded diode half-bridge multilevel inverter topology is presented in symmetric, asymmetric, and cascaded structures

Read more

Summary

A Multilevel Inverter Topology Using Diode Half-Bridge

Jagabar Sathik 1,2 , Shady H. E. Abdel Aleem 3 , Rasoul Shalchi Alishah 4, * , Dhafer Almakhles 1 , Kent Bertilsson 4 , Mahajan Sagar Bhaskar 1 , George Fernandez Savier 2 and Karthikeyan Dhandapani 2 Citation: Sathik, J.; Aleem, S.H.E.A.; Shalchi Alishah, R.; Almakhles, D.; Bertilsson, K.; Bhaskar, M.S.; Fernandez Savier, G.; Dhandapani, K.

Introduction
Proposed Multilevel Inverter Topology
When the diode D1 is conducted and Sy is
Switching
Comparison
The First Algorithm
The Second Algorithm
Total Blocking Voltage
Optimal Topology of the Proposed Multilevel Converter
Number of Voltage Levels with a Constant Number of IGBTs
Number of IGBTs with a Constant Number of Voltage Levels
Number of Voltage Levels with a Constant Number of Sources
Number of Capacitors with a Constant Number of Voltage Levels
Number of Drivers with a Constant Number of Voltage Levels
Number of Diodes with a Constant Number of Voltage Levels
Blocking Voltage Rating with a Constant Number of Voltage Levels
Comparative Study with Recent Cascaded Multilevel Inverter Topologies
The Required Number of IGBTs against the Number of Levels
The Required Number of Driver Circuits against the Number of Levels
Total Blocking Voltage against the Number of Levels
Nearest Level Modulation Technique
Experimental Test Results
Symmetric for 9-Level
Asymmetric Topology for 17-Level Inverter
Cascaded Asymmetric Structure for 25-Level Inverter
8.8.Conclusions
Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call