Abstract
A frequency-locked-loop optimized for output frequency accuracy and locking time is implemented in a 90nm CMOS technology. The output frequency ranges from 7–9.8GHz with a reference frequency at 130MHz. The accuracy of the output frequency is 130ppm, achieved by minimizing and dithering the fine tuning bits of the oscillator. The estimated locking-time is below 50 reference clock cycles, thanks to the frequency locking nature. A binary frequency detector is adopted, lending the FLL naturally to a digital implementation, therefore avoiding the control voltage leakage issue. The measured phase noise @1MHz is −67dBc/Hz. The implementation offers itself a suitable solution for duty-cycled system.
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