Abstract
This paper presents a three-core LC-based digitally controlled oscillator (DCO) in 55 nm CMOS technology for wideband all-digital phased-locked loop (ADPLL) system. Various techniques are employed to ease the trade-off between tuning range, frequency resolution and linearity. Multi cores and multi-stage improved capacitor arrays are implemented to achieve an ultra-wideband tuning range of 91%. Capacitor division technology is employed for high frequency resolution and carefully symmetrical layout arrangement is applied for linear frequency tuning. This DCO oscillates over a 2.7-7.2 GHz frequency range with a fine frequency resolution of 3.2-14.2 kHz. The DCO exhibits a phase noise of -128.7 dBc/Hz at 1 MHz frequency offset from 4.95 GHz carrier. The total area of the DCO is 1.35×1.08 mm2, with a total current consumption of 25 mA from a 2.5 V supply voltage. The simulation results show that the proposed DCO exhibits comparable good tuning range, resolution and phase noise performances, and is suitable for wideband ADPLL application.
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