A MOO‐based Methodology for Designing 3D Stacked Integrated Circuits

Abstract

ABSTRACTIn the past decades, the micro‐electronic industry has been following the Moore's law to improve the performance of integrated circuits (ICs). However, it will probably be impossible to follow this law in the future due to physical limitations appearing with the miniaturization of the transistors below a certain threshold. In order to overcome this problem, new technologies have emerged, and among them the two‐dimensional stacked integrated circuits (3D‐SIC) have been proposed to keep the Moore's momentum alive. 3D‐SICs can bring numerous advantages in the design of future ICs but at the cost of additional design complexity due to their highly combinatorial nature, and the optimization of several conflicting criteria. In this paper, we present a first study of tools that can help the design of 3D‐SICs, using multi‐objective optimization (MOO). Our study has targeted one of the main issues in the design of 3D‐SICs: the floorplanning. This work shows that the use of MOO can provide relevant and objective analysis of the problem that may not be feasible with the current design methods. MOO can allow a quick design space exploration and an improvement of the current design flows. Also, with its flexibility, MOO can cope with the multiple degrees of freedom of 3D‐SICs, which enables more design possibilities. We believe that these promising results will help designers to overcome the main difficulties of designing 3D‐SICs. Copyright © 2013 John Wiley & Sons, Ltd.