Abstract
A hardware monitor for a multi-microprocessor system is presented. This monitor is based on a number of interface cards plugged on the local and global buses of the target machine. Signals are sent to a supervisors CPU that performs data reduction and interpretation, and coordinates the activity of the interface cards. Some special problems arising from the target architecture and from the nature of the available signals are discussed. This monitor is highly modular and can be easily integrated with a software monitor or with the scheduling routines of the target operating system to perform run time tuning operations.
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