Abstract
In the preceding paper [1], a new phenomenological model for the electrical conduction in polycrystalline silicon was developed. Electrical conduction in polycrystalline silicon was shown to be controlled by dopant segregation, carrier trapping, and carrier tunneling through the grain boundaries. In this paper, the theoretical model is compared to experiment. The electrical behavior of polycrystalline silicon is shown to be influenced by the properties of the grain boundaries. In arsenic and phosphorus-doped polycrystalline-silicon films the grain boundaries are best modeled by rectangular barriers with a height of 0.66 eV and an approximate width of 7 A. The width of the grain-boundary barriers and the density of carrier trapping states are found to be weak functions of the dopant species and sample processing. The resistivity is found to be a strong function of dopant concentration, dopant species, and processing history at low and intermediate dopant concentrations, and the model can be used to predict this behavior.
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