A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

Abstract

This article presents a synchronous minimum-skew clock tree synthesis algorithm for single flux quantum circuits considering splitter delays and placement blockages. The proposed methodology improves the state-of-the-art by accounting for splitter delays and creating a fully balanced clock tree structure in which the number of clock splitters from the clock source to all the sink nodes is identical. Additionally, a mixed integer linear programming based algorithm is presented that removes the overlaps among the clock splitters and placed cells (i.e., placement blockages) and minimizes the clock skew, simultaneously. Using the proposed method, the average clock skew for 17 benchmark circuits is 4.6 ps, improving the state-of-the-art algorithm by $\text{70}{\%}$ . Finally, a clock tree synthesis algorithm for imbalanced topologies is presented that reduces the clock skew and the number of clock splitters in the clock network by $\text{56}{\%}$ and $\text{37}{\%}$ , respectively, compared with a fully balanced clock tree solution.