Abstract
This paper presents a new approach to solving the DSP address code generation problem. A minimum cost circulation approach is used to efficiently generate high-performance addressing code in polynomial time. Results show that addressing code size improvements of up to 6/spl times/ are obtained, accounting for up to 1.6/spl times/ improvement in code size and performance of compiler-generated DSP code. This research is important for industry since this value-added technique can improve code size, energy dissipation, and performance, without increasing cost.
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