A Millimeter Wave Loss-Aware Methodology for Switchless PALNA Integrated Circuit Design

Abstract

Phased array element RF front ends typically use single pole double throw switches or circulators with high isolation to prevent leakage of transmit energy into the receiver circuits. However, as phased-array designs scale to the millimeter-wave range, with high degrees of integration, physical size, and performance degradations associated with switches and circulators can present challenges in meeting system performance and SWAP requirements. This paper provides a loss-aware methodology for analysis and design of switchless transmit/receive (T/R) circuits. The methodology provides design insights and a practical, generally applicable approach for solving the multivariable optimization problem of switchless power amplifier/low-noise amplifier (PALNA) matching networks, which present optimal matching impedances to both the PALNA while maximizing power transfer efficiency and minimizing dissipative losses in each T/R mode of operation. An example design in global foundries 32SOI CMOS at W-band using the proposed methodology is presented. The design achieves simulated maximum power added efficiency of 18% in transmit and noise figure of 7.5 dB in receive at 94 GHz.