A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus

Abstract

In this paper, a method to reduce the effect on image quality caused by the parasitic resistance of column bus in high-resolution cMOS image sensors is presented. Through the mathematical model of the column bus, the effect on image quality caused by the resistance is analyzed. The resistance would cause two nonideal factors: dynamic swing reduction and nonlinearity. To reduce the effect of the nonideal factors, this paper utilizes a layout design by putting the readout circuit and column bias circuit on different sides of the pixel array. The relationship among the resistance, light intensity of input, and standard deviation of output gray levels is analyzed. In a 0.13- $\mu \text{m}$ CMOS process and a 12 cm $\times$ 12 cm pixel array, the simulation result shows that the resistance would cause column stripes or gradient under a traditional method. Under the proposed method, the peak standard deviation under uniform illumination decreases from 16.25 to 1.44. The peak signal-to-noise ratio increases from 64.66 to 91.64 dB and the structural similarity index increases from 0.79 to 0.97. The proposed method can enhance image quality for high-resolution image sensors significantly.