Abstract
This article describes an improvement in the noise reduction performance of a column correlated multiple sampling (CMS) readout circuit using interleaved pixel source follower for high-resolution and high-framerate CMOS image sensors (CISs). In this architecture, the time-interleaved operation of the two pixel source followers reduces the restrictions imposed by the settling time of the pixel source followers and extends the time for multiple sampling. The noise analysis indicates that this method has an advantage of enhanced noise reduction not only for thermal noise but also for 1/ f noise when a high-speed readout operation is required. The measurement of the noise performance of the 8K image sensor using the CMS with the interleaved pixel source follower method exhibits a low input-referred noise of 3.2 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> at 8K 120 frames per second, while 4.6 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> with the conventional single-source follower readout method. The measurement results match reasonably well with the analysis presented in this article, demonstrating the effectiveness of the interleaved pixel source follower method for high-resolution and high-framerate CISs.
Highlights
T HE recent trends in video applications have tended toward increasing spatial resolutions, such as 4K, 8K, and high framerates
The noise reduction effect analysis indicated that the increase in the sampling number, owing to the interleaved pixel source followers, tends to be large in the high-resolution CMOS image sensors (CISs), resulting in a large enhancement in noise reduction
The interleaved pixel source follower method has the advantage of enhanced noise reduction performance for thermal noise and for 1/ f noise when a high-speed readout operation is required
Summary
T HE recent trends in video applications have tended toward increasing spatial resolutions, such as 4K, 8K, and high framerates. These include a digital implementation with multiple A/D conversions based on a single slope (SS) [8], [9] and successive approximation register (SAR) [10] ADC and an analog implementation with a passive switched capacitor (SC) [11], [12] and an SC integrator circuit [13], [14] Achieving both high-speed readout and low noise, which are required in high-resolution and high-framerate CISs, is difficult for the CMS readout circuit. This time-interleaved operation reduces the restriction imposed by the settling time of the pixel source followers and extends the time for multiple sampling We applied this method to a column-parallel readout circuit in an 8K image sensor and achieved random noise of 3.2 e− at a readout time of 0.93 μs [8K 120 fps operation with digital correlated double sampling (CDS)] [15]. The contribution of the interleaved pixel source follower method for the noise performance in high-resolution and high-framerate CISs is demonstrated
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