Abstract
SummaryIn this paper, a method for 3 ‐th ( ) harmonics rejection in 6 ‐path filters is proposed, and the related analysis is provided. Using a single‐ended‐input to differential‐output structure, the filter selectivity around even harmonics are also suppressed. Accordingly, a proof‐of‐concept band‐pass filter is designed, and postlayout simulations in the 90‐nm CMOS technology are carried out, which covers an input frequency range from 200 MHz to 1.2 GHz with a channel bandwidth of 10 to 15.5 MHz. The achieved third harmonic rejection at 1‐GHz local oscillator (LO) frequency is about 43 dB. Over the entire radio frequency (RF) range, the in‐band IIP3 and noise figure are better than 1.5 dBm and 5.3 dB, respectively. The power consumption of the analog circuitry is 21 mW from the 1.2‐V supply, whereas the digital clock generation circuitry consumes between 0.9 and 5.2 mW, depending on the center frequency of the filter.
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