A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array

Abstract

In recent years, driven by artificial intelligence (AI) applications, the mesh-connected processor array has become a popular high-performance computing architecture. For these AI chips, the embedded memories occupy more than 2/3 of the overall area, which in turn dominate the yield and reliability of the computing chips. Memory built-in self-repair (MBISR) has been considered as a feasible solution for test and repair of the embedded memories. However, MBISR does not take advantage of the regular topology of the mesh-connected processor array. In this paper, we propose a memory built-in peer-repair (MBIPR) architecture that allows every processor core to share its spare memories with the neighboring cores in the mesh-connected array. Experimental results show that the repair rate of the proposed MBIPR outperforms that of the original MBISR. Compared with MBISR, MBIPR increases the spare utilization by 2.1-8.1 x, and the lifetime by 2.1-7.9 x, with only about 0.2-0.9% higher area overhead.